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? semiconductor components industries, llc, 2011 january, 2011 ? rev. 9 1 publication order number: ncp1200a/d ncp1200a pwm current-mode controller for universal off-line supplies featuring low standby power housed in soic ? 8 or pdip ? 8 package, the ncp1200a enhances the previous ncp1200 series by offering a reduced optocoupler current together with an increased drive capability. due to its novel concept, the circuit allows the implementation of complete off ? line ac ? dc adapters, battery charger or a smps where standby power is a key parameter. with an internal structure operating at a fixed 40 khz, 60 khz or 100 khz, the controller supplies itself from the high ? voltage rail, avoiding the need of an auxiliary winding. this feature naturally eases the designer task in battery charger applications. finally, current ? mode control provides an excellent audio ? susceptibility and inherent pulse ? by ? pulse control. when the current setpoint falls below a given value, e.g. the output power demand diminishes, the ic automatically enters the so ? called skip cycle mode and provides excellent efficiency at light loads. because this occurs at a user adjustable low peak current, no acoustic noise takes place. the ncp1200a features an efficient protective circuitry which, in presence of an overcurrent condition, disables the output pulses while the device enters a safe burst mode, trying to restart. once the default has gone, the device auto ? recovers. features ? no auxiliary winding operation ? auto ? recovery internal output short ? circuit protection ? extremely low no ? load standby power ? current ? mode control with skip ? cycle capability ? internal temperature shutdown ? internal leading edge blanking ? 250 ma peak current capability ? internally fixed frequency at 40 khz, 60 khz and 100 khz ? direct optocoupler connection ? spice models available for transient and ac analysis ? pin to pin compatible with ncp1200 ? pb ? free packages are available typical applications ? ac ? dc adapters for portable devices ? offline battery chargers ? auxiliary power supplies (usb, appliances, tvs, etc.) soic ? 8 d suffix case 751 marking diagrams pin connections pdip ? 8 p suffix case 626 1 8 1 8 1200apyy awl yywwg x = 1, 4, or 6 yy = 40, 60, or 100 a = assembly location l, wl = wafer lot y, yy = year w, ww = work week or g = pb ? free package 1 adj 8 hv 2 fb 3 cs 4 gnd 7 nc 6 v cc 5 drv (top view) miniature pwm controller for high power ac ? dc wall adapters and offline battery chargers see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information http://onsemi.com 200ax alyw 1 8 1 8
ncp1200a http://onsemi.com 2 figure 1. typical application example emi filter universal input + + ncp1200a + v out adj fb cs gnd hv v cc drv 1 2 3 4 8 7 6 5 *please refer to the application information section. 1n4007* pin function description pin no. pin name function pin description 1 adj adjust the skipping peak current this pin lets you adjust the level at which the cycle skipping process takes place. shorting this pin to ground, permanently disables the skip cycle feature. 2 fb sets the peak current setpoint by connecting an optocoupler to this pin, the peak current setpoint is adjusted accordingly to the output power demand. 3 cs current sense input this pin senses the primary current and routes it to the internal comparator via an l.e.b. 4 gnd the ic ground ? 5 drv driving pulses the driver?s output to an external mosfet. 6 v cc supplies the ic this pin is connected to an external bulk capacitor of typically 10 f. 7 nc ? this unconnected pin ensures adequate creepage distance. 8 hv generates the v cc from the line connected to the high ? voltage rail, this pin injects a constant current into the v cc bulk capacitor.
ncp1200a http://onsemi.com 3 figure 2. internal circuit architecture overload? uvlo high and low internal regulator 250 ma hv current source internal v cc 8 7 6 5 hv nc v cc drv 1 2 3 4 q flip ? flop dcmax = 80% q 250 ns l.e.b. 40 ? 60 ? 100 khz clock - + - + 80 k 20 k 57 k 1 v current sense ground fb adj 24 k 25 k + ? v ref reset 1.2 v skip cycle comparator set fault duration 5 v maximum ratings rating symbol value unit power supply voltage v cc 16 v thermal resistance junction ? to ? air, pdip ? 8 version thermal resistance junction ? to ? air, soic version r ja r ja 100 178 c/w c/w maximum junction temperature t j(max) 150 c temperature shutdown ? 145 c storage temperature range ? ? 60 to +150 c esd capability, human body model model (all pins except v cc and hv) ? 2.0 kv esd capability, machine model ? 200 v maximum voltage on pin 8 (hv), pin 6 (v cc ) grounded ? 450 v maximum voltage on pin 8 (hv), pin 6 (v cc ) decoupled to ground with 10 f ? 500 v minimum operating voltage on pin 8 (hv) ? 40 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability.
ncp1200a http://onsemi.com 4 electrical characteristics (for typical values t j = 25 c, for min/max values t j = 0 c to +125 c, max t j = 150 c, v cc = 11 v unless otherwise noted.) characteristic symbol pin min typ max unit dynamic self ? supply (all frequency versions, otherwise noted) v cc increasing level at which the current source turns ? off v cc(off) 6 11.2 12.1 13.1 v v cc decreasing level at which the current source turns ? on v cc(on) 6 9.0 10 11 v v cc decreasing level at which the latchoff phase ends v cc(latch) 6 ? 5.4 ? v internal ic consumption, no output load on pin 5 icc1 6 ? 750 1000 (note 1) a internal ic consumption, 1.0 nf output load on pin 5, f sw = 40 khz icc2 6 ? 1.2 1.4 (note 2) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 60 khz icc2 6 ? 1.4 1.6 (note 2) ma internal ic consumption, 1.0 nf output load on pin 5, f sw = 100 khz icc2 6 ? 1.9 2.2 (note 2) ma internal ic consumption, latchoff phase icc3 6 ? 350 ? a internal startup current source (t j > 0 c, pin 8 biased at 50 v) high ? voltage current source, v cc = 10 v ic1 8 4.0 7.0 ? ma high ? voltage current source, v cc = 0 ic2 8 ? 13 ? ma drive output output voltage rise ? time @ cl = 1.0 nf, 10 ? 90% of output signal t r 5 ? 67 ? ns output voltage fall ? time @ cl = 1.0 nf, 10 ? 90% of output signal t f 5 ? 25 ? ns source resistance r oh 5 27 40 61 sink resistance r ol 5 5.0 10 21 current comparator (pin 5 unloaded unless otherwise noted) input bias current @ 1.0 v input level on pin 3 i ib 3 ? 0.02 ? a maximum internal current setpoint (note 3) i limit 3 0.8 0.9 1.0 v default internal current setpoint for skip cycle operation i lskip 3 ? 360 ? mv propagation delay from current detection to gate off state t del 3 ? 90 160 ns leading edge blanking duration (note 3) t leb 3 ? 250 ? ns internal oscillator (v cc = 11 v, pin 5 loaded by 1.0 k ) oscillation frequency, 40 khz version f osc ? 37 43 48 khz built ? in frequency jittering, f sw = 40 khz f jitter ? ? 350 ? khz oscillation frequency, 60 khz version f osc ? 53 61 68 khz built ? in frequency jittering, f sw = 60 khz f jitter ? ? 460 ? khz oscillation frequency, 100 khz version f osc ? 90 103 114 khz built ? in frequency jittering, f sw = 100 khz f jitter ? ? 620 ? khz maximum duty cycle dmax ? 74 83 87 % feedback section (v cc = 11 v, pin 5 unloaded) internal pullup resistor r up 2 ? 20 ? k pin 3 to current setpoint division ratio i ratio ? ? 3.3 ? ? skip cycle generation default skip mode level v skip 1 0.95 1.2 1.45 v pin 1 internal output impedance z out 1 ? 22 ? k 1. max value at t j = 0 c. 2. maximum value @ t j = 25 c, please see characterization curves. 3. pin 5 loaded by 1.0 nf.
ncp1200a http://onsemi.com 5 typical characteristics 9.6 9.7 9.8 9.9 10.0 10.1 10.2 ? 25 0 25 50 75 100 125 600 650 700 750 800 850 900 ? 25 0 25 50 75 100 125 0 10 20 30 40 50 60 70 ? 25 0 25 50 75 100 125 11.1 11.3 11.5 11.7 11.9 12.1 12.3 12.5 ? 25 0 25 50 75 100 125 0.90 1.10 1.30 1.50 1.70 1.90 2.10 ? 25 0 25 50 75 100 125 38 44 50 56 62 68 74 80 86 92 98 104 110 ? 25 0 25 50 75 100 12 5 temperature ( c) leakage ( a) figure 3. hv pin leakage current vs. temperature temperature ( c) v cc(off) , threshold (v) figure 4. v cc(off) vs. temperature temperature ( c) v cc(on) , (v) figure 5. v cc(on) vs. temperature temperature ( c) icc1 ( a) 100 khz 60 khz 40 khz figure 6. icc1 vs. temperature temperature ( c) icc2 (ma) 100 khz 60 khz 40 khz figure 7. icc2 vs. temperature temperature ( c) f sw (khz) 100 khz 60 khz 40 khz figure 8. switching frequency vs. temperature
ncp1200a http://onsemi.com 6 typical characteristics 1.00 1.05 1.10 1.15 1.20 1.25 1.30 1.35 1.40 ? 25 0 25 50 75 100 125 ? 25 0 25 50 75 100 12 5 temperature ( c) icc3 ( a) 190 220 250 280 310 340 370 400 430 460 490 figure 9. v cc latchoff vs. temperature figure 10. icc3 vs. temperature figure 11. drive and source resistance vs. temperature temperature ( c) current setpoint (v) figure 12. current sense limit vs. temperature temperature ( c) v skip (v) figure 13. v skip vs. temperature figure 14. max duty cycle vs. temperature temperature ( c) v cc latchoff 5.15 5.20 5.25 5.30 5.35 5.40 5.45 5.50 ? 25 0 25 50 75 100 125 temperature ( c) duty max (%) ? 25 0 25 50 75 100 125 temperature ( c) ohm 0 10 20 30 40 50 60 sink source 0.80 0.84 0.88 0.92 0.96 1.00 ? 25 0 25 50 75 100 125 73 75 77 79 81 83 85 87 ? 25 0 25 50 75 100 125
ncp1200a http://onsemi.com 7 application information introduction the ncp1200a implements a standard current mode architecture where the switch ? off time is dictated by the peak current setpoint. this component represents the ideal candidate where low part ? count is the key parameter, particularly in low ? cost ac ? dc adapters, auxiliary supplies, etc. due to its high ? performance high ? voltage technology, the ncp1200a incorporates all the necessary components normally needed in uc384x based supplies: timing components, feedback devices, low ? pass filter and self ? supply. this later point emphasizes the fact that on semiconductor?s ncp1200a does not need an auxiliary winding to operate: the product is naturally supplied from the high ? voltage rail and delivers a v cc to the ic. this system is called the dynamic self ? supply (dss). dynamic self ? supply the dss principle is based on the char ge/discharge of the v cc bulk capacitor from a low level up to a higher level. we can easily describe the current source operation with a bunch of simple logical equations: power ? on: if v cc < vcc h then current source is on, no output pulses if v cc decreasing > vcc l then current source is off, output is pulsing if v cc increasing < vcc h then current source is on, output is pulsing typical values are: vcc h = 12 v, vcc l = 10 v to better understand the operational principle, figure 15?s sketch offers the necessary light: figure 15. the charge/discharge cycle over a 10 f v cc capacitor 10.0 m 30.0 m 50.0 m 70.0 m 90.0 m v cc current source off on output pulses v ripple = 2 v uvlo h = 12 v uvlo l = 10 v the dss behavior actually depends on the internal ic consumption and the mosfets gate charge qg. if we select a mosfet like the mtp2n60e, qg max equals 22 nc. with a maximum switching frequency of 68 khz for the p60 version, the average power necessary to drive the mosfet (excluding the driver efficiency and neglecting various voltage drops) is: f sw ? qg ? v cc with f sw = maximum switching frequency qg = mosfets gate charge v cc = v gs level applied to the gate to obtain the final ic current, simply divide this result by v cc : i driver = f sw ? qg = 1.5 ma. the total standby power consumption at no ? load will therefore heavily rely on the internal ic consumption plus the above driving current (altered by the driver?s efficiency). suppose that the ic is supplied from a 350 vdc line. the current flowing through pin 8 is a direct image of the ncp1200a consumption (neglecting the switching losses of the hv current source). if icc2 equals 2.3 ma @ t j = 25 c, then the power dissipated (lost) by the ic is simply: 350 x 2.3 m = 805 mw. for design and reliability reasons, it would be interesting to reduce this source of wasted power which increases the die temperature. this can be achieved by using different methods: 1. use a mosfet with lower gate charge qg 2. connect pin through a diode (1n4007 typically) to one of the mains input. the average value on pin 8 becomes v mains(peak) 2 . our power contribution example drops to: 223 x 2.3 m = 512 mw. if a resistor is installed between the mains and the diode, you further force the dissipation to migrate from the package to the resistor. the resistor value should account for low ? line startup. 3. permanently force the v cc level above vcc h with an auxiliary winding. it will automatically disconnect the internal startup source and the ic will be fully self ? supplied from this winding. again, the total power drawn from the mains will significantly decrease. make sure the auxiliary voltage never exceeds the 16 v limit.
ncp1200a http://onsemi.com 8 figure 16. a simple diode naturally reduces the average voltage on pin 8 8 7 6 5 1 2 3 4 mains cbulk hv skipping cycle mode the ncp1200a automatically skips switching cycles when the output power demand drops below a given level. this is accomplished by monitoring the fb pin. in normal operation, pin 2 imposes a peak current accordingly to the load value. if the load demand decreases, the internal loop asks for less peak current. when this setpoint reaches a determined level, the ic prevents the current from decreasing further down and starts to blank the output pulses: the ic enters the so ? called skip cycle mode, also named controlled burst operation. the power transfer now depends upon the width of the pulse bunches (figure 18). suppose we have the following component values: lp, primary inductance = 1 mh f sw , switching frequency = 61 khz ip skip = 200 ma (or 333 mv/r sense ) the theoretical power transfer is therefore: 1 2 lp ip 2 f sw 1.2 w if this ic enters skip cycle mode with a bunch length of 20 ms over a recurrent period of 100 ms, then the total power transfer is: 1.2 . 0.2 = 240 mw. to better understand how this skip cycle mode takes place, a look at the operation mode versus the fb level immediately gives the necessary insight: figure 17. skip cycle operation i p(min) = 333 mv/r sense normal current mode operation fb 1 v 4.2 v, fb pin open 3.2 v, upper dynamic range when fb is above the skip cycle threshold (1 v by default), the peak current cannot exceed 1 v/r sense . when the ic enters the skip cycle mode, the peak current cannot go below vpin1 / 3.3. the user still has the flexibility to alter this 1 v by either shunting pin 1 to ground through a resistor or raising it through a resistor up to the desired level. grounding pin 1 permanently invalidates the skip cycle operation. power p1 power p2 power p3 figure 18. output pulses at various power levels (x = 5.0 s/div) p1 p2 p3
ncp1200a http://onsemi.com 9 figure 19. the skip cycle takes place at low peak currents which guaranties noise ? free operation 315.40 882.70 1.450 m 2.017 m 2.585 m 300 m 200 m 100 m 0 max peak current skip cycle current limit we recommend a pin 1 operation between 400 mv and 1.3 v that will fix the skip peak current level between 120 mv / rsense and 390 mv / rsense. non ? latching shutdown in some cases, it might be desirable to shut off the part temporarily and authorize its restart once the default has disappeared. this option can easily be accomplished through a single npn bipolar transistor wired between fb and ground. by pulling fb below the adj pin 1 level, the output pulses are disabled as long as fb is pulled below pin 1. as soon as fb is relaxed, the ic resumes its operation. figure 20 depicts the application example: figure 20. another way of shutting down the ic without a definitive latchoff state on/off q1 8 7 6 5 1 2 3 4
ncp1200a http://onsemi.com 10 power dissipation the ncp1200a is directly supplied from the dc rail through the internal dss circuitry. the average current flowing through the dss is therefore the direct image of the ncp1200a current consumption. the total power dissipation can be evaluated using: (v hvdc ? 11 v) ? icc2. if we operate the device on a 250 vac rail, the maximum rectified voltage can go up to 350 vdc. however, as the characterization curves show, the current consumption drops at high junction temperature, which quickly occurs due to the dss operation. at t j = 50 c, icc2 = 1.7 ma for the 61 khz version over a 1 nf capacitive load. as a result, the ncp1200a will dissipate 350 . 1.7 ma@t j = 50 c = 595 mw. the soic ? 8 package offers a junction ? to ? ambient thermal resistance r ja of 178 c/w. adding some copper area around the pcb footprint will help decreasing this number: 12 mm x 12 mm to drop r ja down to 100 c/w with 35 copper thickness (1 oz.) or 6.5 mm x 6.5 mm with 70 copper thickness (2 oz.). with this later number, we can compute the maximum power dissipation the package accepts at an ambient of 50 c: pmax t jmax t amax r ja 750 mw which is okay with our previous budget. for the dip8 package, adding a min ? pad area of 80 mm of 35 copper (1 oz.), r ja drops from 100 c/w to about 75 c/w. in the above calculations, icc2 is based on a 1 nf output capacitor. as seen before, icc2 will depend on your mosfet?s qg: icc2 icc1 + f sw x qg. final calculation shall thus accounts for the total gate ? charge qg your mosfet will exhibit. the same methodology can be applied for the 100 khz version but care must be taken to keep t j below the 125 c limit with the d100 (soic) version and activated dss in high ? line conditions. if the power estimation is beyond the limit, other solutions are possible a) add a series diode with pin 8 (as suggested in the above lines) and connect it to the half rectified wave. as a result, it will drop the average input voltage and lower the dissipation to: 350 2 1.7 m 380 mw b) put an auxiliary winding to disable the dss and decrease the power consumption to v cc x icc2. the auxiliary level should be thus that the rectified auxiliary voltage permanently stays above 10 v (to not re ? activate the dss) and is safely kept below the 16 v maximum rating. overload operation in applications where the output current is purposely not controlled (e.g. wall adapters delivering raw dc level), it is interesting to implement a true short ? circuit protection. a short ? circuit actually forces the output voltage to be at a low level, preventing a bias current to circulate in the optocoupler led. as a result, the fb pin level is pulled up to 4.2 v, as internally imposed by the ic. the peak current setpoint goes to the maximum and the supply delivers a rather high power with all the associated ef fects. please note that this can also happen in case of feedback loss, e.g. a broken optocoupler. to account for this situation, ncp1200a hosts a dedicated overload detection circuitry. once activated, this circuitry imposes to deliver pulses in a burst manner with a low duty cycle. the system auto ? recovers when the fault condition disappears. during the startup phase, the peak current is pushed to the maximum until the output voltage reaches its target and the feedback loop takes over. this period of time depends on normal output load conditions and the maximum peak current a llowed by the system. the time ? out used by this ic works with the v cc decoupling capacitor: as soon as the v cc decreases from the uvlo h level (typically 12 v) the device internally watches for an overload current situation. if this condition is still present when the uvlo l level is reached, the controller stops the driving pulses, prevents the self ? supply current source to restart and puts all the circuitry in standby, consuming as little as 350 a typical (icc3 parameter). as a result, the v cc level slowly discharges toward 0.
ncp1200a http://onsemi.com 11 driver pulses driver pulses tim e tim e tim e drv v cc 12 v 10 v 5.4 v regulation occurs here internal fault flag fault is relaxed fault occurs here latchoff phase startup phase figure 21. if the fault is relaxed during the v cc natural fall down sequence, the ic automatically resumes. if the fault still persists when v cc reached uvlo l , then the controller cuts everything off until recovery. when this level crosses 5.4 v typical, the controller enters a new startup phase by turning the current source on: v cc rises toward 12 v and again delivers output pulses at the uvlo h crossing point. if the fault condition has been removed before uvlo l approaches, then the ic continues its normal operation. otherwise, a new fault cycle takes place. figure 21 shows the evolution of the signals in presence of a fault. calculating the v cc capacitor as the above section describes, the fall down sequence depends upon the v cc level: how long does it take for the v cc line to go from 12 v to 10 v? the required time depends on the startup sequence of your system, i.e. when you first apply the power to the ic. the corresponding transient fault duration due to the output capacitor charging must be less than the time needed to discharge from 12 v to 10 v, otherwise the supply will not properly start. the test consists in either simulating or measuring in the lab how much time the system takes to reach the regulation at full load. let?s suppose that this time corresponds to 6 ms. therefore a v cc fall time of 10 ms could be well appropriated in order to not trigger the overload detection circuitry. if the corresponding ic consumption, including the mosfet drive, establishes at 1.8 ma for instance, we can calculate the required capacitor using the following formula: t v c i , with v = 2 v. then for a wanted t of 10 ms, c equals 9 f or 22 f for a standard value. when an overload condition occurs, the ic blocks its internal circuitry and its consumption drops to 350 a typical. this happens at v cc = 10 v and it remains stuck until v cc reaches 5.4 v: we are in latchoff phase. again, using the calculated 22 f and 350 a current consumption, this latchoff phase lasts: 296 ms.
ncp1200a http://onsemi.com 12 protecting the controller against negative spikes and turn ? off problems as with any controller built upon a cmos technology, it is the designer?s duty to avoid the presence of negative spikes on sensitive pins. negative signals have the bad habit to forward bias the controller substrate and induce erratic behaviors. sometimes, the injection can be so strong that internal parasitic scrs are triggered, engendering irremediable damages to the ic if they are a low impedance path is offered between v cc and gnd. if the current sense pin is often the seat of such spurious signals, the high ? voltage pin can also be the source of problems in certain circumstances. during the turn ? off sequence, e.g. when the user unplugs the power supply, the controller is still fed by its v cc capacitor and keeps activating the mosfet on and off with a peak current limited by rsense. unfortunately, if the quality coefficient q of the resonating network formed by lp and cbulk is low (e.g. the mosfet rdson + rsense are small), conditions are met to make the circuit resonate and thus negatively bias the controller. since we are talking about ms pulses, the amount of injected charge (q = i x t) immediately latches the controller which brutally discharges its v cc capacitor. if this v cc capacitor is of sufficient value, its stored energy damages the controller. figure 22 depicts a typical negative shot occurring on the hv pin where the brutal v cc discharge testifies for latchup. figure 22. a negative spike takes place on the bulk capacitor at the switch ? off sequence in low v cc conditions, the ncp1200a gate drive signal show an abnormal behavior and can stay high a few tens of milliseconds. this problem can occur at turn ? off but is usually harmless since the bulk capacitor has been discharged by the switching pulses. however, the problem can become worse if high v t mosfets are implemented. be sure that the selected mosfet v t is between 2.0 v (minimum) and 4.0 v (maximum). figure 23 shows the typical operating waveforms. figure 23. if quick v cc depletion is lacking, the drive output can remain high. vfb v cc vgs vbulk = 0
ncp1200a http://onsemi.com 13 a simple and inexpensive solution helps circumventing both problems, negative biasing, and gate high transient. it consists in a solution using one 1n4007 (or two in a series for safety) forcing the v cc capacitor to deplete at the same rate as the bulk capacitor does. figure 24 shows the solution. figure 24. a diode forces the v cc capacitor to quickly discharge at power ? off cv cc 8 7 6 5 1 2 3 4 + cbulk + 3 1n4007 ncp1200a or 1n4007 1n4007 when the bulk naturally depletes at power ? off, the diode brings the v cc down as soon as vbulk drops below v cc . this ensures a clean turn ? off and the above problems go away. v cc vfb vbulk vgs figure 25. the diode addition forces a clean turn ? off sequence both negative biasing and gate high state troubles once implemented, please make sure that your operating waveforms match those of figure 25. that is to say, a bulk level depleting the v cc capacitor at turn ? off. to summarize: 1. wire a diode between v cc and the bulk capacitor as illustrated by figure 24. 2. select a mosfet affected by a standard v t , minimum of 2 v, maximum of 4 v. 3. check that final waveforms match figure 25 signals
ncp1200a http://onsemi.com 14 ordering information device type marking package shipping ? ncp1200ap40 fsw = 40 khz 1200ap40 pdip ? 8 50 units / rail ncp1200ap40g pdip ? 8 (pb ? free) ncp1200ad40r2 200a4 soic ? 8 2500 units / reel ncp1200ad40r2g soic ? 8 (pb ? free) ncp1200ap60 fsw = 60 khz 1200ap60 pdip ? 8 50 units / rail ncp1200ap60g pdip ? 8 (pb ? free) ncp1200ad60r2 200a6 soic ? 8 2500 units /reel ncp1200ad60r2g soic ? 8 (pb ? free) ncp1200ap100 fsw = 100 khz 1200ap100 pdip ? 8 50 units / rail ncp1200ap100g pdip ? 8 (pb ? free) ncp1200ad100r2 200a1 soic ? 8 2500 units / reel ncp1200ad100r2g soic ? 8 (pb ? free) ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d.
ncp1200a http://onsemi.com 15 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint*
ncp1200a http://onsemi.com 16 package dimensions 8 lead pdip case 626 ? 05 issue m 14 5 8 f note 5 d e b l a1 a e3 e a top view c seating plane 0.010 ca side view end view end view note 3 dim min nom max inches a ???? ???? 0.210 a1 0.015 ???? ???? b 0.014 0.018 0.022 c 0.008 0.010 0.014 d 0.355 0.365 0.400 d1 0.005 ???? ???? e 0.100 bsc e 0.300 0.310 0.325 l 0.115 0.130 0.150 ???? ???? 5.33 0.38 ???? ???? 0.35 0.46 0.56 0.20 0.25 0.36 9.02 9.27 10.02 0.13 ???? ???? 2.54 bsc 7.62 7.87 8.26 2.92 3.30 3.81 min nom max millimeters notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: inches. 3. dimension e is measured with the leads re- strained parallel at width e2. 4. dimension e1 does not include mold flash. 5. rounded corners optional. e1 0.240 0.250 0.280 6.10 6.35 7.11 e2 e3 ???? ???? 0.430 ???? ???? 10.92 0.300 bsc 7.62 bsc e1 d1 m 8x e/2 e2 c on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. sc illc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems in tended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scill c and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising ou t of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding th e design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resa le in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1200a/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your loca l sales representative

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